1. Field of the Invention
The present invention relates to a semiconductor memory and, more particularly, to a memory-cell peripheral circuit for raising the operating speed of the semiconductor memory.
2. Description of the Related Art
A known memory cell peripheral circuit in a semiconductor memory is disclosed in "1989, IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS", PP28-29.
FIG. 4 shows the arrangement of this memory-cell peripheral circuit in the prior art.
Referring to the figure, numerals 201 and 202 indicate PMOSFETs of low driving ability which are normally "on", and numerals 401 and 402 indicate PMOSFETs of high driving ability.
The PMOSFETs 201, 202, 401 and 402 constitute a data line load circuit. Applied to the data-line load circuit is a write enable signal WEa 340, which is set at a "high" level in a write mode and at a "low" level at any other time. Symbol WL 120 denotes a word line. A memory cell MC 121 is configured of PMOSFETs 101 and 102, and NMOSFETs 103, 104, 105 and 106. Symbols DL 123 and DL 122 denote a pair of data lines which are opposite in polarity to each other, and which are respectively connected to common write lines CW 342 and CW 343 through writing column switches 403 and 404. By the way, in this specification, a signal X shall express a signal which is opposite in polarity to a signal X.
In addition, the data lines DL 123 and DL 122 are respectively connected to common read lines CR 129 and CR 130 through reading column switches 113 and 114. A column select signal Yi 131 is applied for controlling the reading column switches 113 and 114. Shown at numeral 405 is an inverter circuit which receives the column select signal Yi 131 as an input, and the output signal of which controls the writing column switches 403 and 404.
A write enable signal WEb 341 is similar to the signal WEa 340. Write data DIN 125 is directly input to a write driver 407, while it is input to a write driver 406 through an inverter circuit 408 for producing the inverted signal of this write data.
In the circuit shown in FIG. 4, the data is written into the memory cell in such a way that the memory cell MC 121 to be accessed is selected by setting the word line WL 120 at the high level and the column select signal Yi 131 at the low level, and that the write enable signals WEa 340 and WEb 341 are changed from the low level to the high level.
When the write enable signal WEb 341 has become the high level, the data items are propagated to the common write lines CW 342 and CW 343 by the respective write drivers 406 and 407.
That is, in a state in which the common write lines CW 342 and CW 343 are both initially at the high level, the signal of only one of them changes to the low level. Then, the data items of the common write lines CW 342 and CW 343 are respectively written into the memory cell MC 121 through the corresponding writing column switches 403 and 404 and data lines DL 123 and DL 122.
When the data items are to be written, the write enable signal WEa 340 is also changed from the low level to the high level. This is intended to turn "off" the PMOSFETs of high driving ability 401 and 402 which pulls up the respective data lines DL 123 and DL 122 to the high level and thereby making it easy for the potentials of these data lines to be changed to the low level. Thus, the data writing mode is quickened, and the conflict between the data-line load circuit and the write drivers 406, 407 can be prevented from occurring in the data writing mode.
When the write mode has ended, the write enable signals WEa 340 and WEb 341 are changed from the high level to the low level. Thus, the common write lines CW 342 and CW 343 are both changed to the high level. Also the data lines DL 123 and DL 122 are recovered from the low level in the write mode to the high level in an ordinary read mode by the data-line load circuit at numerals 201, 202, 401 and 402.
According to the prior-art circuit thus far explained, the two control signals of the write enable signals WEa 340 and WEb 341 are required for the write control. The write enable signal WEa 340 must simultaneously turn "on" or "off" the PMOSFETs 401 and 402 which are large in size and provided in sets of two in each column and which total a large number for all the column. Therefore, the load capacitance of the write enable signal WEa 340 is large, and the delay time thereof is not negligible.
The time delay has resulted in the problem that the "on" and "off" controls of the PMOSFETs 401 and 402 slow down.
Besides, the delay of the write enable signal WEa 340 has posed the problem of lengthening a time period for writing the data into the memory cell MC 121 and the recovery time period of the data lines DL 123 and DL 122, immediately after the writing. The reason for this therefor is that a time at which the data writing into the memory cell is started, and the recovery start time of the data lines DL 123 and DL 122, immediately after the writing, are determined by a slower one of the write enable signals WEa 340 and WEb 341. Incidentally, the longer recovery time period of the data lines DL 123 and DL 122 also extends a read time period at the next timing which immediately succeeds the writing of the data into the memory cell.
Further, the delay of the write enable signal WEa 340 incurs the timing deviation thereof relative to the write enable signal WEb 341. This has led to the problem that, in the case of writing the data items, the conflict between the PMOSFETs 401, 402 and the write drivers 406, 407 is brought about, so through currents flow from the data-line load circuit to the write drivers.
Incidentally, reference materials relevant to memory-cell peripheral circuits in semiconductor memories are "1988, IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS", PP186-187, and "IEEE 1991, CUSTOM INTEGRATED CIRCUITS CONFERENCE", PP10.4.1-10.4.4.
Meanwhile, the memory cells, as stated above, are stated above are generally included in RAMs. In the RAM, the memory cells are arranged in the shape of a matrix, and data is read out from or written into the memory cell designated by an input address.
There has also been known a semiconductor memory in which a memory cell from which data is to be read out is not designated by an input address, but that a coincidence between search data, afforded as an input, and a stored content, as predetermined data is examined, and the memory cell is designated by the examined result so as to read out the data from a RAM.
Such a semiconductor memory is called a "CAM (Content Addressable Memory)". The semiconductor memory of this type includes separately from the RAM for storing data to-be-read-out, a CAM cell array which is configured of memory cells for storing contents for a coincidence search, as well as coincidence search circuits for detecting the coincidence between the search data and the stored contents of the memory cells.
A known circuit arrangement of such a CAM cell array is disclosed in the official gazette of Japanese Patent Application Laid-open No. 119096/1988.
This circuit arrangement includes a coincidence detection circuit and a voltage/current conversion circuit which are disposed for every group consisting of a plurality of memory cells for storing the same bits of stored data items. It realizes the coincidence search between search data and stored data in the following way: One memory cell corresponding to a word designated by a word line is selected from among the plurality of memory cells, the bit value of the selected memory cell is read out and has its coincidence detected with the value of the same bit of the search data, and the result of the detection is converted into current. Such currents of all the bits of the data are subjected to an OR operation.
In this regard, the coincidences between the search data and all the stored data items need to be detected in CAMs which are applied to a full associative cache memory, etc. Since, however, the prior-art circuit arrangement is furnished with one coincidence detection circuit in correspondence with the plurality of memory cells, it must compare the bit values of the search data and all the stored data items successively while changing over the memory cells through the word lines, in order to detect the coincidences thereof. This has been a significant drawback in terms of the speed of the coincidence detections.
It is therefore considered to furnish each memory cell with the coincidence detection circuit and the voltage/current conversion circuit for the purpose of realizing the coincidence detections between the search data and all the stored data items through one time of operation.
Since, however, the prior-art circuit arrangement operates to read out the data from each memory cell and to detect the coincidence however, the data read out from the memory cell is of small voltage. In order to derive a predetermined current from the voltage, therefore, bipolar transistors of large-sized MOSFETs must be employed for the voltage/current conversion circuit. In view of an increase in a circuit area, accordingly, it is not practical to furnish each memory cell with the voltage/current conversion circuit.
Another known circuit arrangement of the CAM cell array type in the prior art, is disclosed in "IEEE, 1989, CUSTOM INTEGRATED CIRCUITS CONFERENCE", PP10.2.1-10.2.5.
This circuit arrangement is outlined in FIG. 14.
Referring to FIG. 14, the circuit arrangement includes data lines DL 1010 and DL 1011, a word line WL 1012, a PMOSFET 4001 for precharging a match line ML 4300, and an inverter circuit 4200 for waveshaping and for driving a load. Symbol CK 4400 denotes a clock signal.
A memory cell 1100 is configured of a flip-flop which is constituted by inverter circuits 1103 and 1104, and NMOSFETs 1101 and 1102 which are turned "on" in the read and write modes of the memory cell. A coincidence search circuit 4100 is configured of NMOSFETs 4101, 4102, 4103 and 4104. Numeral 4105 indicates the ground potential of the circuitry.
A CAM cell 5200 is constructed of the memory cell 1100 and the search circuit 4100.
In the time period of the low level of the clock signal CK 4400, the match line ML 4300 is precharged to the high level by the PMOSFET 4001.
On the other hand, in the time period of the high level of the clock signal CK 4400, whether the potential of the match line is to maintain the high level or to fall to the low level is determined depending upon the result of the comparison between search data and the stored data of the memory cell.
That is, the potential of the match line ML 4300 maintains the high level on condition that the stored data of the memory cell 1100 and the search data, namely, the data items of the data lines DL 1010 and DL 1011 are coincident, whereas it falls to the low level on condition that they are noncoincident.
This type of circuit arrangement, however, does not take into consideration that, as a bit width to be simultaneously searched broadens more, the load of the match line ML 4300 for delivering the searched result as an output becomes heavier.
More specifically, the match line ML 4300 is fully swung from the level of a supply voltage to the level of the ground potential. Therefore, in the case where the match line ML 4300 is heavily loaded, a long time is expended in charging/discharging it. This has posed a problem in point of the operating speed of the CAM.
Herein, in order to quickly charge/discharge the match line ML 4300, the PMOSFET 4001 and the MOSFETs constituting the coincidence search circuit 4100, as shown in FIG. 14, must have their gate widths enlarged. This expedient, however, increases the load of the match line still more. Eventually, there has been the problem that the high operating speed and the high integration density of the semiconductor memory are not compatible.
Incidentally, a CAM cell array is also disclosed in "IEEE, 1991, CUSTOM INTEGRATED CIRCUITS CONFERENCE", PP10.2.1-10.2.4.